Semiconductor storage device

ABSTRACT

A semiconductor storage device includes: a plurality of memory array cells (hereinafter, referred to as cells); a circuit arranged in each of the cells for precharge of each bit line of the cells to a predetermined voltage; and a circuit for comparing, for each bit line, an output voltage of each bit line of the cells selected for reading out data to an output voltage of each bit line of cells selected for reference. When the data is read out, the voltage value for precharge of the bit line of the cells selected for reading out data and the voltage value for precharge of the bit line of the cells selected for reference are temporarily set to different values. Thus, all the output bits of the cells selected for reading out data can be read out by a single read out operation.

TECHNICAL FIELD

The present invention relates to a semiconductor storage device. Morespecifically, the present invention relates to read operation from anonvolatile semiconductor storage device such as a flash memory orEEPROM.

BACKGROUND ART

As an example of a conventional nonvolatile semiconductor storagedevice, a flash memory will be described below. An example of an outlineof the configuration of a conventionally common flash memory is shown inFIG. 5.

In this example, each memory array cell 51 is composed of a large numberof flash memory elements, and feeds the outputs of 1,024 bit lines to amultiplexer 52. Each multiplexer 52 is, on its output side, connected tosense amplifiers 53 that are provided one for every 128 bit lines. Thatis, each multiplexer 52 is, on its output side, connected to eight senseamplifiers 53. To the inverting input terminal of each sense amplifier53 is connected a reference cell 54 that outputs a reference current.Here, each sense amplifier 53 is built as a current-to-voltageconversion amplifier.

This conventional flash memory includes a plurality of circuit blockseach including a memory array cell 51, a multiplexer 52, senseamplifiers 53, and reference cells 54 (FIG. 5 shows only two suchcircuit blocks).

In a read operation from the conventional flash memory shown in FIG. 5,first, from among the plurality of memory array cells, one with which toperform the read operation is selected, and the selected memory arraycell then transfers the data stored therein to the multiplexer via 1,024bit lines. The multiplexer 52 then outputs one chunk after another ofthe data fed thereto from the memory array cell to the individual senseamplifiers 53. Each sense amplifier 53 then compares the referencecurrent fed from the reference cell 54 with the current fed from themultiplexer, and outputs a voltage that is commensurate with thedifference between those currents.

In the flash memory shown in FIG. 5, eight sense amplifier are providedfor each memory array cell, and a read operation is performed asdescribed above. Consequently, a single read operation accomplishes thereading of as little as eight-bit data.

By providing more sense amplifiers for each memory array cell, it ispossible to increase the number of data bits that can be read in asingle read operation. This, however, is undesirable from the viewpointof compactness because the sense amplifiers, which are of thecurrent-to-voltage conversion type, require a large circuit area. Hence,it is unpractical to provide more than 16 sense amplifiers for eachmemory array cell. This limits the number of data bits that can be readfrom a conventional flash memory in a single read operation to eight tosixteen. This is the reason that read operation tends to be slow withconventional flash memories.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a semiconductor storagedevice that permits fast read operation.

To achieve the above object, according to the present invention, asemiconductor storage device is provided with: a plurality of memoryarray cells; precharge circuits, provided one for each memory arraycell, for precharging each bit line of the memory array cell with apredetermined voltage; and a comparing circuit for comparing, for eachbit line, the output voltage of each bit line of the memory array cellcurrently being selected for a data read operation and the outputvoltage of each bit line of the memory array cell currently beingselected as a reference. Here, in the data read operation, the voltagewith which the bit line of the memory array cell selected for the dataread operation is precharged and the voltage with which the bit line ofthe memory array cell selected as the reference is precharged are madetemporarily different.

With this configuration, all the output bits (for example, 1,024 bits)of the main array cell currently being selected for a data readoperation can be read in a single read operation. Consequently,semiconductor storage devices according to the present invention permitdramatically faster read operation than conventional ones, which permitonly eight to sixteen bits to be read in a single read operation.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing an example of an outline of theconfiguration of a nonvolatile memory according to the invention.

FIG. 2 is a time chart showing the signal waveforms observed at relevantpoints in the nonvolatile memory shown in FIG. 1.

FIG. 3 is a diagram showing an example of the configuration of the senseamplifier provided in the nonvolatile memory shown in FIG. 1.

FIG. 4 is a diagram showing another example of the configuration of thesense amplifier provided in the nonvolatile memory shown in FIG. 1.

FIG. 5 is a diagram showing an example of an outline of theconfiguration of a conventional flash memory.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be describedwith reference to the drawings. The following descriptions deal with, asan example of a semiconductor storage device according to the invention,a nonvolatile memory such as a flash memory or EEPROM. FIG. 1 shows anexample of an outline of the configuration of a nonvolatile memoryaccording to the invention, assuming that it is given a memory sizecomparable with that of the conventional flash memory.

Of all memory array cells, those in which data to be read is present arehereinafter referred to as main array cells. Each main array cell 2 has1,024 nonvolatile memory cells 3. Each bit line of the main array cell 2is connected to one of the output terminals of a precharge circuit 1.That is, the precharge circuit 1 has 1,024 output terminals. Each bitline of the main array cell 2 is also connected through a P-channelMOSFET (metal-oxide-semiconductor field-effect transistor) 4 to thenon-inverting input terminal of a sense amplifier 21.

Likewise, the memory array cell 12 with which to compare the main arraycell 2 has 1,024 nonvolatile memory cells 13. Each bit line of thememory array cell 12 is connected to one of the output terminals of aprecharge circuit 11. That is, the precharge circuit 11 has 1,024 outputterminals. Each bit line of the memory array cell 12 is also connectedthrough a P-channel MOSFET 14 to the inverting input terminal of a senseamplifier 21.

The precharge circuit 1 receives a precharge signal Φ_(P) and a 1Vprecharge signal PR_(S), and the precharge circuit 11 receives theprecharge signal Φ_(P) and a 1V precharge signal PR_(D). The P-channelMOSFETs 4 and 14 each receive, at their gates, a selection signal SELn(where n is an integer number fulfilling 1≦n≦1,024). All the memorycells 3 within the main array cell 2 each receive, at their controlgates, a word line signal WL_(S), and all the memory cells 13 within thememory array cell 12 each receive, at their control gates, a word linesignal WL_(D). Moreover, an operation control signal SEN for switchingthe sense amplifiers 21 between an operating and a non-operating stateis fed to each of the sense amplifiers 21.

The sense amplifiers 21 are each built as a voltage amplifier thatoutputs a voltage signal obtained by amplifying the difference betweenthe two input voltages thereto. Thus, the sense amplifiers 21 require asmaller circuit area than the current-to-voltage conversion amplifiersused in the conventional flash memory. For the sake of simplicity, FIG.1 shows only one circuit block (hereinafter referred to as a basiccircuit) that is configured as described above, including the prechargecircuit 1, main array cell 2, P-channel MOSFETs 4, precharge circuit 11,memory array cell 12, P-channel MOSFETs 14, and sense amplifiers 21. Inreality, the nonvolatile memory according to the invention includes aplurality of such basic circuits, of which one is selected at a timewith the selection signal SELn. The sense amplifiers may be shared amongthe plurality of basic circuits so that the nonvolatile memory as awhole has n or m sense amplifiers (where m is a natural numberfulfilling m≦n). In this case, to the input terminal of each senseamplifier are connected a plurality of P-channel MOSFETs, and theseP-channel MOSFETs function as a multiplexer.

Next, how a read operation is performed in the nonvolatile memoryaccording to the invention shown in FIG. 1 will be described withreference to FIG. 1 and the time chart shown in FIG. 2. The followingdescription discusses the operation performed when the m-th data bit(where m is a natural number fulfilling m≦n) is read from the memoryarray cells 2 and 12. In the following description and in FIG. 2,indications of “m” are omitted.

Before the read operation, the precharge signal Φ_(P), the 1V prechargesignal PR_(S), the 1V precharge signal PR_(D), the word line signalWL_(S), the word line signal WL_(D), the selection signal SEL, theoperation control signal SEN, and the output signal are all low.

The precharge signal Φ_(P) and the selection signal SEL turn from low tohigh at time point t1, and remain high up till time point t8, when theyturn low, and thereafter remain low. Accordingly, the bit line signalsBL_(S), the voltage signals DIO_(S), the bit line signals BL_(D), andthe voltage signals DIO_(D) are all significant during the period fromt1 to t8, and remain indefinite during the rest of time.

The 1V precharge signal PR_(S) for the side of the memory array cellfrom which data is read (i.e., the main array cell 2 (this applieswherever applicable)) turns from low to high at time point t3, andremains high up till time point t6, when it turns from high to low, andthereafter remains low. On the other hand the 1V precharge signal PR_(D)for the side of the memory array cell from which no data is read (i.e.,the memory array cell 12 (this applies wherever applicable)) remains lowthroughout.

The precharge circuit 1 outputs 0.5 V when the precharge signal Φ_(P) ishigh and simultaneously the 1V precharge signal PR_(S) is low, andoutputs 1 V when the precharge signal Φ_(P) is high and simultaneouslythe 1V precharge signal PR_(S) is high. On the other hand, the prechargecircuit 11 outputs 0.5 V when the precharge signal Φ_(P) is high andsimultaneously the 1V precharge signal PR_(D) is low, and outputs 1 Vwhen the precharge signal Φ_(P) is high and simultaneously the 1Vprecharge signal PR_(D) is high.

The word line signal WL_(S) for the side of the memory array cell fromwhich data is read gradually increases starting at time point t2,becomes high at time point t3, remains high up till time point t6, thengradually decreases starting at time point t6, becomes low at time pointt7, and thereafter remains low.

Accordingly, if a given memory cell 3 within the memory array cell fromwhich data is read has data written thereto, the memory cell does notturn on, with the result that the bit line signal BL_(S) and the voltagesignal DIO_(S) remain 0.5 V during the period from t1 to t3, rise to 1 Vat time point t3, then remain 1 V up till time point t6, then graduallydecrease starting at time point t6 until they reach 0.5 V, andthereafter remain 0.5 V. By contrast, if a given memory cell 3 withinthe memory array cell from which data is read has no data writtenthereto, the memory cell turns on, with the result that the bit linesignal BL_(S) and the voltage signal DIO_(S) remain 0.5 V during theperiod from t1 to t2, then gradually decrease starting at time point t2,reach 0 V at time point t3, remain 0 V up till time point t6, thengradually increase starting at time point t6, reach 0.5 V at time pointt7, and then remain 0.5 V up till the time point t8 (for the period fromt2 to t7, see the broken line in FIG. 2).

The word line signal WL_(D) for the side of the memory array cell fromwhich no data is read remains low throughout. Accordingly, irrespectiveof whether a given memory cell 13 has data written thereto or not, thebit line signal BL_(D) and the voltage signal DIO_(D) remain 0.5 Vduring the period from t1 to t8.

The operation control signal SEN is high only during the period from t4to t5. Accordingly, reading a memory cell having data written theretowithin the memory array cell from which data is read causes the outputsignal OUT_(m) (where m is a natural number fulfilling 1≦m≦n) to remainhigh only during the period from t4 to t5. By contrast, reading a memorycell having no data written thereto within the memory array cell fromwhich data is read leaves the output signal OUT₁ (where l is a naturalnumber fulfilling 1≦l≦n) to remain low also during the period from t4 tot5 (for the period from t4 to t5, see the broken line in FIG. 2).

In this way, it is possible to read, in a single read operation, all theoutput bits of the memory array cell from which data is read. That is,in this embodiment, it is possible to read n-bit data in a single readoperation. Specifically, it is possible to read, for example, 1,024-bitdata at a time. In a case where data is read from the memory array cell12 that is connected to the inverting input terminals of the senseamplifiers, by inverting the output signals OUT_(n) with inverters, itis possible to obtain signals similar to the output signals obtainedwhen data is read from the main array cell 2 that is connected to thenon-inverting input terminals of the sense amplifiers. In this case, itis from the memory array cell 12 that data is read, and therefore thememory array cell 12 behaves as a main memory cell. The descriptionsabove deal with a case where 1,024-bit data is handled. Needless to say,data having any other number of bits may be handled instead. The presentinvention helps effectively reduce the circuit area when applied to, inparticular, a flash memory, which is a kind of nonvolatile memory.However, the present invention may be applied also to a memory that isnot nonvolatile, i.e., to a volatile memory. An example of theconfiguration of a volatile memory according to the invention can beobtained by replacing the memory cells 3 and 12 in the nonvolatilememory shown in FIG. 1 with volatile memory cells.

Next, practical examples of the configuration of the sense amplifier 21will be described. An example of the configuration of the senseamplifier 21 is shown in FIG. 3. A terminal to which a constant voltageV_(CC) is applied is connected to the source of a P-channel MOSFET 31and to the source of a P-channel MOSFET 32. The gate of the P-channelMOSFET 31 and the gate of the P-channel MOSFET 32 are connectedtogether. The gate and drain of the P-channel MOSFET 31 are connectedtogether.

The drain of the P-channel MOSFET 31 is connected to the drain of anN-channel MOSFET 33. The drain of the P-channel MOSFET 32 is connectedto a terminal from which the output signal OUT_(n) is outputted and tothe drain of an N-channel MOSFET 34.

A terminal that serves as the non-inverting input terminal (+) of thesense amplifier is connected to the gate of the N-channel MOSFET 33. Aterminal that serves as the inverting input terminal (−) of the senseamplifier is connected to the gate of the N-channel MOSFET 34.

The source of the N-channel MOSFET 33 and the source of the N-channelMOSFET 34 are connected together, and are connected to the drain of anN-channel MOSFET 35. The gate of the N-channel MOSFET 35 is connected toa terminal to which the operation control signal SEN is fed. The sourceof the N-channel MOSFET 35 is grounded.

Another example of the configuration of the sense amplifier 21 is shownin FIG. 4. In FIG. 4, such circuit elements as are found also in FIG. 3are identified with common reference numerals, and their detailedexplanations will be omitted. The sense amplifier shown in FIG. 4differs from the sense amplifier shown in FIG. 3 in the followingrespects. In the sense amplifier shown in FIG. 3, the gate of theP-channel MOSFET 31 and the gate of the P-channel MOSFET 32 areconnected together. By contrast, in the sense amplifier shown in FIG. 4,the gate of the P-channel MOSFET 31 is connected to the node at whichthe drain of the P-channel MOSFET 32, the terminal from which the outputsignal OUT is outputted, and the drain of the N-channel MOSFET 34 areconnected together; the gate of the P-channel MOSFET 32 is connected tothe node at which the drain of the P-channel MOSFET 31 and the drain ofthe N-channel MOSFET 33 are connected together; and the gate and drainof the P-channel MOSFET 31 are not connected together.

INDUSTRIAL APPLICABILITY

Nonvolatile memories according to the present invention find applicationin computers and the like.

1. A semiconductor storage device comprising: a plurality of memoryarray cells; precharge circuits, provided one for each memory arraycell, for precharging each bit line of the memory array cell with apredetermined voltage; and a comparing circuit for comparing, for eachbit line, an output voltage of each bit line of the memory array cellcurrently being selected for a data read operation and an output voltageof each bit line of the memory array cell currently being selected as areference, wherein, in the data read operation, the voltage with whichthe bit line of the memory array cell selected for the data readoperation is precharged and the voltage with which the bit line of thememory array cell selected as the reference is precharged are madetemporarily different.
 2. The semiconductor storage device of claim 1,wherein the comparing circuit is built as a plurality of voltageamplifiers.
 3. The semiconductor storage device of claim 1, wherein aswitch element is provided between each memory array cell and thecomparing circuit so that whether the memory array cell is selected orunselected is switched as a result of the switch element being turned onor off.
 4. The semiconductor storage device of claim 3, wherein aplurality of basic circuits are provided that each comprise theplurality of memory array cells, the precharge circuits, the comparingcircuit, and the switch element, and the comparing circuit is sharedamong the plurality of basic circuits.
 5. The semiconductor storagedevice of claim 1, wherein the memory array cells are flash memorycells.
 6. The semiconductor storage device of claim 2, wherein thememory array cells are flash memory cells.
 7. The semiconductor storagedevice of claim 3, wherein the memory array cells are flash memorycells.
 8. The semiconductor storage device of claim 4, wherein thememory array cells are flash memory cells.